HYB18TC256160BF-3S

high-speed Double-Data- Rate-Two CMOS DRAM, 2.3 V, 2μA, BGA

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Price:: US $1.60~1.76 / piece [Get Latest Price]

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	US $1.60~1.76

PartNumber:: HYB18TC256160BF-3S

Brand:: Qimonda AG - Qimonda | Pack: BGA | D/C: 09+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-07-26

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Part Number:HYB18TC256160BF-3S
US $1.60 - 1.76
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Product Summary

The HYB18TC256160BF-3S is a high-speed Double-Data- Rate-Two CMOS DRAM device containing 536,870,912 bits and internally configured as a quad -bank DRAM. The HYB18TC256160BF-3S is organized as either 8 Mbit ×8 I/O ×4 banks or 4 Mbit ×16 I/O ×4 banks chip. The HYB18TC256160BF-3S achieves high speed transfer rates starting at 400 Mb/sec/pin for general applications.

Parametrics

HYB18TC256160BF-3S absolute maximum ratings: (1)VDD Voltage on VDD pin relative to VSS: –1.0 to +2.3 V; (2)VDDQ Voltage on VDDQ pin relative to VSS: –0.5 to +2.3 V; (3)VDDL Voltage on VDDL pin relative to VSS: –0.5 to +2.3 V; (4)VIN, VOUT Voltage on any pin relative to VSS:–0.5 to +2.3 V; (5)TSTG Storage Temperature: –55 to +100 °C.

Features

HYB18TC256160BF-3S features: (1)1.8 V ± 0.1 V Power Supply; (2)1.8 V ± 0.1 V (SSTL_18)compatible I/O; (3)DRAM organizations with 8 and 16 data in/outputs; (4)Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation; (5)Programmable CAS Latency: 3, 4, 5 and 6; (6)Programmable Burst Length: 4 and 8; (7)Differential clock inputs (CK and CK); (8)Bi-directional, differential data strobes (DQS and DQS)are transmitted / received with data. Edge aligned with read data and center-aligned with write data.; (9)DLL aligns DQ and DQS transitions with clock; (10)DQS can be disabled for single-ended data strobe operation; (11)Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS; (12)Data masks (DM)for write data; (13)Posted CAS by programmable additive latency for better command and data bus efficiency.