SC16C550BIB48

Product Summary

The SC16C550BIB48 is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The SC16C550BIB48 can handle serial data rates up to 3 Mbit/s. The SC16C550BIB48 also provides DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C550BIB48 operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range, and is available in plastic DIP40, PLCC44 and LQFP48 packages.

Parametrics

SC16C550BIB48 absolute maximum ratings: (1)VCC supply voltage: 7 V; (2)Vn voltage at any pin: GND: - 0.3 to VCC + 0.3 V; (3)Tamb operating temperature: -40 to +85 ℃; (4)Tstg storage temperature: -65 to +150 ℃; (5)Ptot(pack)total power dissipation per package: 500 mW.

Features

SC16C550BIB48 features: (1)5 V, 3.3 V and 2.5 V operation; (2)Industrial temperature range; (3)After reset, all registers are identical to the typical 16C450 register set; (4)Capable of running with all existing generic 16C450 software; (5)Picompatibility with the industry-standard ST16C450/550, TL16C450/550, PC16C450/550; (6)Up to 3 Mbit/s transmit/receive operatioat 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V; (7)16 byte transmit FIFO; (8)16 byte receive FIFO with error flags; (9)Programmable auto-RTS and auto-CTS; (10)u Iauto-CTS mode, CTS controls transmitter; (11)u Iauto-RTS mode, RxFIFO contents and threshold control RTS; (12)Automatic hardware flow control; (13)Software selectable Baud Rate Generator; (14)Four selectable Receive FIFO interrupt trigger levels; (15)Standard modem interface; (16)Standard asynchronous error and framing bits (Start, Stop, and Parity OverruBreak); (17)Independent receiver clock input; (18)Transmit, Receive, Line Status, and Data Set interrupts independently controlled.

Diagrams